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| HAF1008(L), HAF1008(S) Silicon P Channel MOS FET Series Power Switching REJ03G0027-0100Z Rev.1.00 May.13.2003 Description This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of high junction temperature like applying over power consumption, over current etc. Features * * * * Logic level operation (-4 to -6 V Gate drive) High endurance capability against to the short circuit Built-in the over temperature shut-down circuit Latch type shut-down operation (Need 0 voltage recovery) Outline LDPAK D G Gate resistor Temperature Sencing Circuit Latch Circuit Gate Shutdown Circuit 1 2 1 2 3 3 1. Gate 2. Drain (Flange) 3. Source S Rev.1.00, May.13.2003, page 1 of 11 HAF1008(L), HAF1008(S) Absolute Maximum Ratings (Ta = 25C) Item Drain to source voltage Gate to source voltage Gate to source voltage Drain current Drain peak current Symbol VDSS VGSS VGSS ID ID (pulse) Note1 Ratings -60 -16 2.5 -20 -40 -20 50 150 -55 to +150 Unit V V V A A A W C C Body-drain diode reverse drain IDR current Channel dissipation Channel temperature Storage temperature PchNote2 Tch Tstg Notes: 1. PW 10s, duty cycle 1 % 2. Value at Tc = 25C Typical Operation Characteristics (Ta = 25C) Item Input voltage Input current (Gate non shut down) Symbol VIH VIL IIH1 IIH2 IIL Input current (Gate shut down) Shut down temperature Gate operation voltage IIH(sd)1 IIH(sd)2 Tsd Vop Min -3.5 -- -- -- -- -- -- -- -3.5 Typ -- -- -- -- -- -0.8 -0.35 175 -- Max -- -1.2 -100 -50 -1 -- -- -- -12 Unit V V A A A mA mA C V Vi = -8 V, VDS = 0 Vi = -3.5 V, VDS = 0 Vi = -1.2 V, VDS = 0 Vi = -8 V, VDS = 0 Vi = -3.5 V, VDS = 0 Channel temperature Test Conditions Rev.1.00, May.13.2003, page 2 of 11 HAF1008(L), HAF1008(S) Electrical Characteristics (Ta = 25C) Item Drain current Drain current Drain to source breakdown voltage Gate to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Symbol Min ID1 ID2 -7 -- Typ -- -- -- -- -- -- -- -- -- -0.8 -0.35 -- -- 18.5 60 42 865 5.7 26 6.5 9 -0.9 100 1.84 1 Max -- -10 -- -- -- -100 -50 -1 100 -- -- -10 -2.15 -- 80 54 -- -- -- -- -- -- Unit A mA V V V A A A A mA mA A V S m m pF s s s s V ns ms ms IF = -20 A, VGS = 0 IF = -20 A, VGS = 0 diF/dt = 50A/s VGS = -5 V, VDD = -16 V VGS = -5 V, VDD = -24 V Test Conditions VGS = -3.5 V, VDS = -2 V VGS = -1.2 V, VDS = -2 V ID = -10 mA, VGS = 0 IG = -800 A, VDS = 0 IG = 100 A, VDS = 0 VGS = -8 V, VDS = 0 VGS = -3.5 V, VDS = 0 VGS = -1.2 V, VDS = 0 VGS = 2.4 V, VDS = 0 VGS = -8 V, VDS = 0 VGS = -3.5 V, VDS = 0 VDS = -60 V, VGS = 0 VDS = -10 V, ID = -1 mA ID = -10 A, VDS = -10 V Note3 ID = -10 A, VGS = -4 V Note3 ID = -10 A, VGS = -10 V Note3 VDS = -10 V, VGS = 0, f = 1 MHz VGS = -10 V, ID= -10 A, RL = 3 V(BR)DSS -60 V(BR)GSS -16 V(BR)GSS 2.5 IGSS1 IGSS2 IGSS3 IGSS4 -- -- -- -- -- -- -- -1.1 10 -- -- -- -- -- -- -- -- -- -- -- Input current (shut down) Zero gate voltage drain current Forward transfer admittance IGS(OP)1 IGS(OP)2 IDSS Gate to source cutoff voltage VGS(off) |yfs| Static drain to source on state RDS(on) resistance RDS(on) Output capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time Over load shut down Note4 operation time Coss td(on) tr td(off) tf VDF trr tos1 tos2 Notes: 3. Pulse test 4. Include the time shift based on increasing of channel temperature when operate under over load condition. Rev.1.00, May.13.2003, page 3 of 11 HAF1008(L), HAF1008(S) Main Characteristics Power vs. Temperature Derating 80 Pch (W) -500 -200 (A) Maximum Safe Operation Area Thermal shut down operation area 60 -100 -50 -20 -10 -5 -2 -1 -0.5 -0.3 DC PW 10 1 Drain Current ID Channel Dissipation 0 s 40 s Op m er at = 20 Operation in this area is limited by RDS(on) ion 10 (T m s c= 25 C ) -50 -100 Ta = 25C -0.5 -1 -2 -5 -10 -20 0 50 100 150 Tc (C) 200 Case Temperature Drain to Source Voltage VDS (V) -50 Typical Output Characteristics -10 V -8 V -6 V (A) -20 Typical Transfer Characteristics Drain Current ID (A) -40 -5 V -4 V -20 VGS = -3.5 V -10 Pulse Test 0 -2 -4 -6 -8 -10 Drain to Source Voltage VDS (V) -16 -30 Drain Current ID -12 -8 Tc = -25C -4 25C 75C V DS = -10 V Pulse Test 0 -1 -2 -3 -4 -5 Gate to Source Voltage VGS (V) Rev.1.00, May.13.2003, page 4 of 11 HAF1008(L), HAF1008(S) Drain to Source Saturation Voltage vs. Gate to Source Voltage Pulse Test Drain to Source On State Resistance VDS(on) (m) Drain to Source Saturation Voltage VDS(on) (V) Static Drain to Source Sate Resistance vs. Drain Current 200 Pulse Test 100 V GS = -4 V 50 -10 V -1 -0.8 -0.6 I D = -10 A -0.4 -5 A -0.2 20 10 -0.1 -0.2 -0.5 -1 -2 -5 -10 -20 -50 0 -2 -4 -6 -8 -10 Gate to Source Voltage VGS (V) Drain Current ID (A) Drain to Source On State Resistance RDS(on) (m) Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance vs. Temperature 100 Pulse Test I D = -10 A 80 V GS = -4 V 60 -5 A -10 A -5 A Forward Transfer Admittance vs. Drain Current 50 20 10 5 75C 2 1 0.5 -0.1 -0.2 -0.5 -1 -2 -5 -10 -20 -50 V DS = -10 V Pulse Test Tc = -25C 25C 40 -10 V 20 0 -25 0 25 50 75 100 125 150 Tc (C) Case Temperature Drain Current ID (A) Rev.1.00, May.13.2003, page 5 of 11 HAF1008(L), HAF1008(S) Body to Drain Diode Reverse recovery Time 500 100 Switching Characteristics Reverse Recovery Time trr (ns) Switching Time t (s) 50 tr 20 10 5 2 1 0.5 VGS = -10 V, VDD = -30 V PW = 300 s, duty < 1 % -0.5 -1 -2 -5 -10 -20 -50 200 100 50 tf t d(off) t d(on) 20 10 -0.1 -0.2 -0.5 -1 di / dt = 50 A / s V GS = 0, Ta = 25C -2 -5 -10 -20 -50 -0.1 -0.2 Reverse Drain Current IDR (A) Drain Current ID (A) Reverse Drain Current vs. Source to Drain Voltage Typical capacitance vs. Drain to Source Voltage 10000 Reverse Drain Current IDR (A) -20 Pulse Test VGS = -5 V -12 0V -8 Capacitance C (pF) -16 1000 -4 100 -0.4 -0.8 -1.2 -1.6 -2.0 0 Source to Drain Voltage VSD (V) VGS = 0 f = 1 MHz -10 -20 -30 -40 -50 -60 Drain to Source Voltage VDS (V) 0 Rev.1.00, May.13.2003, page 6 of 11 HAF1008(L), HAF1008(S) Gate to Source Voltage vs. Shutdown Time of Load-Short Test -20 Shutdown Case Temperature Tc (C) VGS (V) Shutdown Case Temperature vs. Gate to Source Voltage 200 -15 180 Gate to Source Voltage 160 -10 -16 V V DD= -24 V -5 140 120 100 0 I D = -5 A 0 100 1m 10 m -2 -4 -6 -8 VGS (V) -10 Shutdown Time of Load-Short Test Pw (S) Gate to Source Voltage Normalized Transient Thermal Impedance vs. Pulse Width 3 Normalized Transient Thermal Impedance s (t) 1 D=1 0.5 0.2 Tc = 25C 0.3 0.1 0.05 0.1 ch - c(t) = s (t) * ch - c ch - c = 2.50C/W, Tc = 25C PDM PW T 0.0 0 .01 h 2 uls e D= 0.03 PW T 1s p ot 0.01 10 100 1m 10 m Pulse Width PW (S) 100 m 1 10 Rev.1.00, May.13.2003, page 7 of 11 HAF1008(L), HAF1008(S) Switching Time Test Circuit Vin Monitor D.U.T. RL 90% Vin -10 V 50 V DD = -30 V Vout td(on) 90% 10% tr td(off) 90% 10% tf Vout Monitor Vin 10% Switching Time Waveform Rev.1.00, May.13.2003, page 8 of 11 HAF1008(L), HAF1008(S) Package Dimensions As of January, 2003 Unit: mm (1.4) 4.44 0.2 10.2 0.3 1.3 0.15 11.3 0.5 0.3 10.0 + 0.5 - 8.6 0.3 1.3 0.2 1.37 0.2 0.76 0.1 2.54 0.5 2.54 0.5 11.0 0.5 0.2 0.86 + 0.1 - 2.49 0.2 0.4 0.1 Package Code JEDEC JEITA Mass (reference value) LDPAK (L) -- -- 1.40 g Rev.1.00, May.13.2003, page 9 of 11 HAF1008(L), HAF1008(S) As of January, 2003 Unit: mm 4.44 0.2 10.2 0.3 (1.4) 8.6 0.3 + 0.3 - 0.5 10.0 (1.5) (1.5) 2.49 0.2 0.2 0.1 + 0.1 - 7.8 7.0 2.2 1.37 0.2 0.3 3.0 + 0.5 - 1.3 0.2 2.54 0.5 0.2 0.86 + 0.1 - 0.4 0.1 2.54 0.5 Package Code JEDEC JEITA Mass (reference value) LDPAK (S)-(1) -- -- 1.30 g Rev.1.00, May.13.2003, page 10 of 11 1.7 1.3 0.15 7.8 6.6 HAF1008(L), HAF1008(S) Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.1.00, May.13.2003, page 11 of 11 |
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